Z-Plane Link Products Provide a

High Performance Interconnect and Packaging System

For Point-To-Point Serial Systems

The planar, two-dimensional nature of printed circuit board backplanes is the source of many of many design constraints for standard data-com and telecom systems.  The multi-layer board is a method of adding some dimensionality to the system, but the vias and fine lines required for routing circuitry through a multi-layer board are a source of many of the signal integrity problems now being encountered at high speeds, including attenuation and excessive system noise.  Eliminating the two-dimensional constraints of the planar printed circuit board opens up opportunities for alternative design possibilities which improve performance and reduce cost.

A new three-dimensional interconnect technology makes possible the elimination of all signal via stubs and also removes the trace width routing restrictions common to most trace routing schemes by using the space behind the board, the "z-plane" space, to allow traces to expand to widths greater than the space between via holes that is possible for traces routed on the same plane as the via hole structure.  It also allows for the traces to be run in a microstrip configuration.  These factors result in lower signal attenuation and improved crosstalk characteristics.

Instead of a multiple signal layers stacked between ground planes with the connector terminals perforating those layers, signals are routed from connector to connector on narrow orthogonal two-layer pcbs (the Z-Plane Link) which run across in a plane normal to the plane of a typical backplane.  In point-to-point serial system the Z-Plane Link runs across the rear side of the backplane at an angle that is related to the connector and slot pitch and interconnects the various points of the meshed network.  The matched impedance interconnection is made between the narrow pcb and the backplane using a connector or adapter, which also orients the narrow pcb to accommodate the specific angle required for interconnection.

The interconnection system design should extend the use of the existing connector systems well beyond their theoretical limits, since most of the signal integrity issues of impedance matched connectors reside in the printed circuit board interface (vias).  The direct matched impedance connection to the header by the circuit element eliminates some of these problems and allows for improvement of others.. 

The low-loss, impedance controlled signal path has been designed to accommodate bandwidths beyond 10GB/s.  The new system design concept emphasizes low-cost as well as compatibility with legacy systems and component design.  The design is compatible with PICMG 3.0 (Advanced TCA) and is intended to be compliant with the IEEE 802.3ap 10GBASE-KR standard.  Preliminary test data shows that the system can perform beyond 10 Gb/s using standard FR4 substrates and conventional manufacturing technology.

The system is scalable in configuration, size and performance, such that the basic system hardware can remain constant throughout the lifetime of the design concept.  The highly engineered standard circuit elements of the system have advantages, since the difficulty of design and layout of complex multi-layer systems is reduced.  New materials and processes can be introduced with much less technical risk.  Prototyping of new systems is simplified, since new interconnect elements can be developed independently from the system.  Once a single element is characterized, it only requires different lengths to build an entire system.  In comparison, the development of multi-layer boards, which are unique, complex and interactive structures typically require complete re-engineering with each design cycle.

This interconnection and packaging system represents a practical approach to solving the problems of high bandwidth electrical packaging.  It uses conventional materials, processes and connector designs to accomplish these ends, and does it in a way that not only can improves the system performance, but has the potential for reducing both engineering and manufacturing costs.  It can accommodate a variety of network configurations including legacy systems and is scalable in size and performance well into the future.